`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    20:19:14 09/20/2021 
// Design Name: 
// Module Name:    counting 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module counting(
	input [1:0] num,
	input clk,
	output ans);

`define S0 2'b00
`define S1 2'b01
`define S2 2'b10
`define S3 2'b11

reg [1:0] state;

initial begin
	state <= `S0;
end

assign ans = (state == `S3) ? 1'b1 : 1'b0;

always @(posedge clk) begin
	case (state)
		`S0: begin
			if (num == 2'b01) begin
				state <= `S1;
			end else begin
				state <= `S0;
			end
		end  
		`S1: begin
			if (num == 2'b10) begin
				state <= `S2;
			end else if (num == 2'b01)begin
				state <= `S1;
			end else begin
				state <= `S0;
			end
		end
		`S2: begin
			if (num == 2'b11) begin
				state <= `S3;
			end else if (num == 2'b10) begin
				state <= `S2;
			end else begin
				state <= `S1;
			end
		end
		`S3: begin
			if (num == 2'b11) begin
				state <= `S3;
			end else if (num == 2'b01) begin
				state <= `S1;
			end else begin
				state <= `S0;
			end
		end
	endcase
end

endmodule
